Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to technology for easily adjusting a timing between an internal clock and a command in a gear down mode of a memory device.
A next generation semiconductor memory device such as a DDR4 memory device may employ a gear down mode which will be described below.
The target operating speed of a DDR4 memory device is 3,200 Mbps. In such a high speed operation, it may be difficult to achieve a high productivity while ensuring a setup/hold margin between a command and a clock. Thus, a memory device may use an internal clock whose frequency is lowered to half the frequency of data clocks (CK, CK#). This mode is called a gear down mode.
The use of the gear down mode may increase a pulse width of the internal clock because the frequency of the internal clock is lowered to half the frequency of the data clocks. Hence, the setup/hold margin may be ensured up to the level of a 1,6000-Mpbs memory device. However, since the internal clock is not a full rate clock, information on the relationship between a command and a clock may be lost. Therefore, a timing adjusting between an internal clock and a command may be required in order to compensate the lost of information on the relationship between the command and the clock.
FIG. 1 is a timing diagram illustrating a gear down mode after an initial power-up of a memory device.
The memory device may begin a power-up in the gear down mode in which an internal clock INTERNAL_CLK has half the frequency of data clocks CK and CK#. After the power-up of the memory device, a reset signal RESET# may be deactivated to a high level and a clock enable signal CKE may be activated to a high level. This situation may represent that a rank inside the memory device is selected. Before the memory device is set by a mode register setting, it is necessary to know at which edge the internal clock INTERNAI_CLK is aligned by comparison with the data clocks CK and CK#, and it is necessary to know at which edge the internal clock INTERNAL_CLK is aligned with the command. A sync pulse may be used to get such information.
The sync pulse may be applied via a pad through which a chip select signal CS# is inputted.